User Guide: DSim User Manual

DSim is a Hardware Description Language (HDL) simulator developed by Metrics Design Automation.

The simulator supports Verilog, SystemVerilog and VHDL.

NOTE: In order to use the DSim commands found in this User Manual through the DSim Cloud CLI, you must wrap the command options in single quotes. For more information, see User Guide: DSim Cloud CLI Tool simulator commands.

NOTE: In order to use the DSim commands found in this User Manual when working on-prem, you must set the DSIM_LICENSE environment variable to be the path and filename of your license file. For more information on how to generate a license, see Licensing.

Glossary of Terms

Command Line Interface

Common Options
Setting Options by Scope Using Specification File
Language Conformance Options
Constraint Solver Options
Coverage Options

Input Filenames
Compile Once, Run Multiple Times
Using Libraries and Configurations

Running A Simulation

Stages Of A Simulation
Running A Verilog Simulation
Running A VHDL Simulation

Merging and Viewing Coverage

Merging and Viewing Coverage

Library Management

Managing libraries

Waveforms

Dumping/Opening Waveforms

Verification Component Support

Using UVM

Programing Interface Support

Using the DPI and PLI
Using VHPI

Profiling

Profiling

Transparent Compression

Transparent Compression

Using IEEE1735 Encryption

IEEE 1735 Encryption

Notes on DSim treatment of string characters

Lexical Conventions

Notes on DSim treatment of SystemVerilog

Design and Verification Building Blocks
Scheduling Semantics
Delay Modeling
Data Types
LRM Extensions

Notes on DSim treatment of VHDL

Integral Arithmetic

Frequently Asked Questions

FAQ

Supporting Documentation

Release Highlights
Known Issues/Limitations
Legalese: Licenses and Attributions