User Guide: DSim Scheduling Semantics

During development the following code was found to be problematic:

reg reset;

initial begin
  reset = 1'b0;
  #100;
  reset = 1'b1;
  ...
end

always @(posedge clk or negedge reset) begin
  ...
end

The code in question expected to see a reset at time zero, before the first clock edge.

Prior to the event simulation starting, the initial value of reset is 1'bx. Two processes are then scheduled at time zero:

• The initial block will set reset to 1'b0" at time zero.
• The always block will execute its event blocking statement, and block on either clk or reset.

It is not defined which happens first. If the initial block runs first, then the always block will not see a reset at time zero. On the other hand, if the always block runs first, then it will.

DSim now identifies always blocks that immediately block waiting for events, and schedules them to run at time zero before initial blocks and always blocks for which this determination cannot be made. For maximum portability, code like this should be avoided.