User Guide: DSim Major Release Highlights

All Language Reference Manual references are noted with the following abbreviations:

• SV-LRM : SystemVerilog Language Reference Manual IEEE Std 1800™-2023
• VHDL-LRM-2008 : VHDL Language Reference Manual IEEE Std 1076™-2008
• VHDL-LRM-2000 : VHDL Language Reference Manual IEEE Std 1076™-2000

This document covers the highlights of each major release. There are often many patch releases between major releases for which detailed release notes can be found here: DSim Release Notes.

Version: 20240923.0.0

New Features in 2023 version of the SystemVerilog LRM, IEEE Std 1800™-2023

Tolerance Ranges

A value range can now also be specified using the absolute tolerance token +/- or the relative tolerance token +%-.

SV-LRM Reference: 11.4.13 Set membership operator

SV-LRM Reference: 19.5 Defining coverage points

Support user-defined nettypes with tran/tranif0/tranif1

The SystemVerilog LRM, IEEE Std 1800™-2023, describes enhanced support for tran devices wrt to user-defined nettypes. DSim now supports the described functionality.

SV-LRM Reference: 28.8 Bidirectional pass switches (refined in IEEE Std 1800™-2023)

Support for $timeunit, $timeprecision system tasks

The SystemVerilog LRM, IEEE Std 1800™-2023, introduced system tasks $timeunit, $timeprecision. DSim supports these

SV-LRM Reference: 20.4 Timescale system tasks and system functions

Proxy Server Support

You can use the environment variable https_proxy to tell DSim to go through a proxy server when checking for a license.

For example, if your proxy server uses the localhost's port 8080, set the https_proxy environment variable to be https://127.0.0.1:8080.

Custom UVM support

Using your own custom uvm package is now supported by DSim by specifying -uvm <path>.

There are some DSim Cloud considerations. Please see DSim Using Verification Frameworks for more details.

New Command Line Options

These commandline options have been added:

Option	Description
-show-ld	Show the linking command used to link the image after compilation.
-io_dir	Specifies a path to record all files read and written to by each executable in the DSim product family

Action Blocks Instrumented for Block Coverage.

Action blocks are now included in the line coverage counts when DSim collects block coverage.

Version: 20240422.0.0

VHDL released

Previously VHDL support was considered to be Beta, now it is fully released for VHDL-LRM extensions:

• IEEE Std 1076™-2008
• IEEE Std 1076™-2000

IEEE 1735

Support was added for IEEE 1735 version 3. See IEEE 1735 Encryption for more details.

Additional DSim encryption key

It is recommended a 4096 key is used for encryption. There is a new encryption key for DSim with key_keyname="DSim_4k". DSim's original key_keyname="DSim" is still supported however, moving to the new key is recommended.

For more details see IEEE 1735 Encryption

New License Server

DSim supports licensing for DSim Destop by using the DSIM_LICENSE environment variable to point to the user generated license file.

UVM installation directory moved

The installation directory of DSim has changed wrt uvm. The uvm installations can now be found in the following locations:

• $DSIM_HOME/uvm/1.2
• $DSIM_HOME/uvm/1.1d
• $DSIM_HOME/uvm/1.1b

This is only important if existing scripts set $UVM_HOME to a specific version and expected the old directory structure. In that case the paths need to be updated.

Alternatively, to fix this issue please consider using DSim command line option -uvm <ver> instead. See Using Verification Frameworks for details.

Version: 20240129.0.0

Randsequence

DSim now supports the randsequence statement for random sequence generation.

SV-LRM Reference: 18.17 Random sequence generation—randsequence

More semantic checks

Adds additional semantic checks for assignments and references to members of dynamic variables

SV-LRM Reference: 6.21 Scope and lifetime

Profiling

Profiling has been improved in presentation and reporting quality.

The -profile option now takes a level which is used to adjust the aggregation level of the reports.

For more information see Profiling

Some Forcing Restrictions lifted

Previously DSim did not support:

• forcing of variables which were passed through ref port
• forcing of members of unpacked structs

These 2 limitations have been lifted, others still remain. Please see Known Issues for details on the remaining limitations.

Version: 20230925.0.0

VPI forcing of bit-select/part-select of variables.

The SystemVerilog LRM permits forcing of singular variables. Strictly speaking, unpacked arrays and words thereof, or individual bits of a variable cannot be forced. DSim has supported such forces for some time, but the 2023925 extends this capability to the VPI. New flags +acc+WF have been added to request instrumentation for word-level (unpacked array) W and bit-level variable forcing F.

SV-LRM Reference: 10.6.2 The force and release procedural statements

wait_order

DSim now supports the wait_order construct.

SV-LRM Reference: 15.5.4

Performance Improvements

Elaborating instances with a large number of generate blocks is now faster.

Code generation of instances with a large number of simple gate, switch, and pull devices is now faster.

SystemVerilog hierarchical references into VHDL hierarchy

Basic support has been added for accessing VHDL signals using SystemVerilog hierarchical identifiers. Read-only access to an entire signal is supported; writing, indexing, slicing and selection is not.

VPI Enhancements

Support was added for accessing and iterating over structure and union members with vpiMember.

SV-LRM Reference: 37

Multiple Libraries

In flows where multiple DSim libraries are created simultaneously (in parallel) the first step should to prepare the work/library directory to prevent a race condition. To do this use dlib prep

Compiling C/C++ Files

To aid in debugging/understanding of DSim compiling C/C++ files a verbose command line option has been added. The option-cc-verbose will output each compile command before it is executed.

Version: 20230515.0.0

Default zero delay handling

The scheduling of update events has changed for an explicitly specified zero propagation delay through primitives (gates, switches, UDPs), nets, and continuous assignments. Such update events are scheduled in the Active/Reactive region. In past, in order to get the same behaviour, you needed to specify the -opt-zdelay option.

In previous releases, the aforesaid update events were scheduled to the Inactive/Re-Inactive region. It was found that such a behaviour doesn't conform to the SV-LRM.

The deprecated -opt-zdelay option will be removed in the future.

Note that the scheduling of events hasn't changed for an explicitly specified zero delay control in procedural code.

SV-LRM Reference: 4.4.2.3 Inactive events region

SV-LRM Reference: 28.16 Gate and net delays

Version: 20230116.0.0

Integrated support for UVM

dvlcom and dsim both support a -uvm <version> option.

For dvlcom and dsim the necessary UVM directories are automatically included in the search path.

For dsim the necessary SV UVM package is included in the elaborated image and the needed UVM DPI libraries are included for the simulation.

Added Language Conformance Options

-allow-fwd-pkg will allow references to items in packages declared later in the code relaxing SystemVerilog LRM rules.

VHDL 2008 Predefined Attributes

Added support for some attributes new in 2008 including:

• Support for item'value at elaboration time
• Support for item'instance_name at elaboration time
• Support for item'path_name at elaboration time

Support for libary looking using a search path.

Dependant libraries are still looked up through the local work directory (both local and mapped) but can now also be found using a search path DSIM_FE_PATH. As with typical search paths, one or more existing directories separated by a : are expected.

Can be investigated using the dlib command.

Support for encryption of VHDL source files

Added a new command line utility dvhencrypt to encrypt source VHDL files with custom encryption keys.

Decryption of VHDL files has been included since the introduction of VHDL support.

Full support for array/record element constraints (VHDL)

Array and record element constraints are now fully supported.

Support for running simulation in read-only directories

The new -cov-db filename option can specify where the coverage database is written. This, along with the existing -l logname option enable simulation output to be redirected to another directory so a simulation can be run in a read-only directory.

Version: 20220822.0.0

Partial support for array element constraints (VHDL)

Array element constraints are supported as long as the final array type is fully constrained. Subprogram parameters of partially constrained array types are not supported.

Elaboration-time support for access types

Support for functions that allocate/deallocate values for access types now supported during elaboration

VHDL-LRM-2008 Reference: 5.4

Elaboration-time evaluation of non-static constant initializers

Support for declaring constants at the design element level whose initializers are not globally static, e.g. to impure functions that read data from a file.

VHDL-LRM-2008 Reference: 6.4.2.2, 9.4.3 note 2

Elaboration-time support for file types and textio

Support for writing (possibly impure) functions that use file types and/or call textio functions.

VHDL-LRM-2008 Reference: 5.5, 16.4

Generic-mapped packages:

Packages can have generics and be instantiated in various places.

VHDL-LRM-2008 Reference: 4.7, 4.9

Enhanced Generate

Support for cascading if-else clauses for if-generate, as well as a case-generate.

VHDL-LRM-2008 Reference: 11.8, 3.4.2.

New Generics

VHDL2008 supports type generics, which allow for assignment and comparison on otherwise opaque types.

Various constructs also support subprogram and package generics.

VHDL-LRM-2008 Reference: 6.5.3, 6.5.4, 6.5.5

Generic-mapped subprograms

Subprograms can now take generics and be instantiated in various new places.

VHDL-LRM-2008 Reference: 4.2.1, 4.4

Reading outputs

VHDL2008 supports reading from a port of mode out.

VHDL-LRM-2008 Reference: 6.5.6.3

Better support for signal attributes (VHDL)

A number of issues relating to signal attributes were addressed.

Better support for signal aliases (VHDL)

A number of issues relating to signal aliases were addressed.

Version: 20220328.0.0

VHDL ambiguity/overload resolution explanation

The -explain command line argument will produce a report tracing resolution of any name that results in no viable alternatives, or is ambiguous for some expression.

VHDL arithmetic modes:

The range of integer is now -2 ** 31 to 2 ** 31-1 for VHDL2008 and earlier, and is -2 ** 63 to 2 ** 63-1 for VHDL2019. Previously it was 64 bits for all language versions.

The command line option -vhdl-no-ov-chk can be used for both analysis and elaboration to disable generation of runtime code that performs arithmetic overflow checking.

Block coverage for VHDL code

In addition to Verilog and SystemVerilog code, block coverage can now be collected for VHDL code.

VHDL statements

Conditional variable assignments, selected variable assignments and matching case statements are now supported for VHDL2008 and later.

VHDL inertial port mappings

Beginning in VHDL2008 port maps can have complex expressions for the actual. When this occurs there is an implicit inertial delay. DSim now supports this functionality as well as allowing the inertial keyword on simple expressions, resulting in the same delay.

VHDL-LRM-2008 Reference: 6.5.6.3

VHDL process sensitive to all

Processes can now be made sensitive to all signals used by statements within the process by including the all keyword introduced in VHDL2008.

VHDL-LRM-2008 Reference: 11.3

Functional coverage

An empty bin is associated with no values, sequences, or cross-product. By default, empty bins are not saved to the coverage database.

In past, empty bins were saved to the coverage database, which has a potential to cause a run-time performance penalty. If the previous behaviour and performance of DSim is desired, please specify -fcov-save-empty-bins.

Instantiation depth

The command line argument -max-inst-depth controls the depth of any path in the hierarchy. This is used to detect unterminated recursive instantiation.

Version: 20211122.0.0

VHDL Beta

Beta Version: Software and results are provided as is and should be used for testing purposes only

VHDL-LRM extensions:

• IEEE Std 1076™-2008
• IEEE Std 1076™-2000

Line buffering default change

The default DSim setting is to force the buffering of stdout stream upto the next newline. As a result, the relative order of stdout and stderr is preserved whenever both are redirected to the same file. In past, in order to get the same behaviour, you needed to specify -linebuf option.

The change has the potential to cause a run-time performance penalty, in particular for verbose simulations. If the previous behaviour and performance of DSim is desired, please specify -no-linebuf.

If -linebuf was already in use, then this change will have no impact, and no change is required on your end.

Version: 20210621.0.0

Stochastic Analysis And Function Support

DSim now supports the managing of queues and the stochastic queuing models.

The set of system tasks and system functions available are:

 

$q_initialize(q_id, q_type,max_length, status);
$q_add(q_id, job_id, inform_id, status);
$q_remove(q_id, job_id, inform_id, status);
$q_full(q_id , status );
$q_exam(q_id, q_stat_code, q_stat_value, status);

 

SV-LRM Reference: 20.16

License Expiration Information

DSim will now print the license expiration information into the log file at startup.

Exit Codes for Usage Meter

When DSim execution is terminated due to licensing or usage meter issues it will return the following exit codes:

 

EXIT_USAGE_NO_LICENSE       100
EXIT_USAGE_NO_CONNECTION    101
EXIT_USAGE_TOO_MANY_FAILS   102                          
EXIT_USAGE_BAD_MESSAGE      103

 

Additionally more diagnostic information including timestamps is now printed when there are licensing and usage meter problems.

Coverpoint Enable

Coverpoint expressions are no longer evaluated if a corresponding iff expression is false. Previously they were always evaluated, but the values were not sampled if the enable was false. This change impacts expressions such as:

 

cp: coverpoint instr_i.data iff (instr_i != null)

 

which would fault on a null reference otherwise. The change will also impact any testbench where coverpoint expressions have side-effects.

SV-LRM Reference: 19.5

Library Map Search Order

Given a lib.map file of the form:

 

library V2_LIB submodule.v2.sv;
library V3_LIB submodule.v3.sv;

 

The inferred library search order is now equivalent to -L work L V2_LIB -L V3_LIB for compatibility with other vendors. Previously it was -L V2_LIB -L V3_LIB -L work (i.e. work appeared last instead of first).

SV-LRM Reference: 33.4.1.5

Virtual Interface Self-Reference

The name of a virtual interface can now be used to refer to the current instance of the interface, much in the same way that this refers to the current instance of an object.

 

package P;
    function void register_if(virtual foo_if vif);
    ...
    endfunction
endpackage

interface foo_if;
import P::*;
initial register_if(foo_if); // registers current instance
endinterface

 

SV-LRM Reference: 25

Constraint Solver

Array types can now be used for solve...before constraint variables.

SV-LRM Reference: 18.5.10

Synchronous drive of aggregate data types

DSim now supports a field-select/indexing-select/slice-select name in clockvar_expression (used as a target of the synchronous drive). Such an expression may refer to an unpacked structure, an unpacked array, or any part thereof.

SV-LRM Reference: 14.16

Version: 20210322.0.0

Reseeding

The new command line argument -reseed allows a simulation to be reset with a new seed value at a given timestep.

Bug fixes and Performance Improvements

Consolidation of numerous internal bug fixes and some performance improvements in both runtime and memory usage.

Version: 20201123.0.0

Treatment of Compilation Unit Scope

Clause 3.12.1 requires that tools support both possible models for compilation-unit scope: one scope for the entire design, and one scope per compilation unit. Previous versions of DSim supported only the first model. Starting with 20201123 relase, both models are supported, selected by the -shared-unit-scope or -separate-unit-scopes respectively.

SV-LRM Reference: 3.2.1

Selectively Enabling Top-Level Modules

Modern verification methodologies such as UVM allow the user to compile all tests cases into a single image, and then select a test at run time. An older methodology is to compile the design and testbench along with a testcase module, and then run it. A fresh compile is required to run a different test case, which can be time consuming.

As an alternative, DSim allows multiple testcase modules to be compiled alongside a common testbench and design, using a single compile. At run time, one or more of these testcase modules can be enabled.

New options have been added to support this.

• -compile-top name(s) - Compile one or more modules as a run-time selectable top-level instance.
• -run-top name(s) - Enable top-level instances previously compiled.

For more details see "Selectively Enabling Top-Level Modules" in the user manual.

Compiled Libraries with DVlcom

This release introduces the ability to compile SystemVerilog code into libraries as a step separate from elaboration and design image generation. Using the new dvlcom tool, souce code can be analyzed and stored into libraries of cells, which DSim can later use to find definitions of modules and other design elements.

Managing Libraries Using DLib

The dlib utility is used to perform various maintenance tasks on libraries created with the DVlcom.

For details see "Managing Libraries Using dlib in the user manual.

Dynamic Array Parameters

Parameters of dynamic array type are now supported.

Command line options

-debug-verbose category[:...] prints debug information for one or more specified categories. Separate categories with ':' signs. The categories are: pp - preprocessing, hier - instance hierarchy, lib - library maps.

-pp-verbose is deprecated in favour of -debug-verbose pp.

The deprecated options -line-cov, -line-cov-scope-specs, -expr-cov, -toggle-cov and -toggle-cov-scope-specs file have been removed. The options -code-cov and -code-cov-scope-specs file can be used in their place.

-code-cov-scope-specs file can now apply to expression coverage as well as other coverage types.

SystemVerilog Assertions

DSim supports passing of event expressions as actual arguments in named sequences and properties.

In the past, a formal argument in a sequence or property declaration that is used as part of a clocking event or disable condition expression, has required a net or variable reference as an actual argument. This limitation is lifted now.

SV-LRM Reference: 16

Version: 20200720.0.0

Implicitly Specialized Virtual Interfaces

The SV-LRM prohibits the use of interfaces that "contain hierarchical references to objects outside its body or ports that reference other interfaces" as virtual interfaces. DSim upholds this restriction. Starting from this release, the option -allow-ext-vif will permit such interfaces to be used as virtual interfaces, for the purpose of calling tasks and functions of such interfaces using the virtual interface handle. Access to variables and other items in the interface is still disallowed.

SV-LRM reference: 25.9

Enhanced Crash Handling

In the unfortunate event that DSim should crash, the error message attempts to provide more information. In some cases, a description of the item that was being elaborated at the time of the crash can be given. Please provide all such messages to support personnel.

DPI Task Export

DPI task exports are now supported. Please be aware that DPI task exports imply concurrency from the viewpoint of the C programmer, using mechanisms not defined in the SV-LRM. Your code must be thread-safe.

SV-LRM reference: 35.8

C Language Support

Command line option '-c_opts' and '-ld_opts' have been renamed '-c-opts' and '-ld-opts';

Code Coverage

The command line options -line-cov, -toggle-cov and -expr-cov have been deprecated. The option -code-cov should be used to enable code coverages.

The command line options -toggle-cov-scope-specs and -line-cov-scope-specs have been deprecated and replaced by -code-cov-scope-specs.

Force/release of entire unpacked arrays

Force and release statements should only be used on singular data types according to the SV-LRM, however to support customer requirements, dsim now allows force/release statments on entire unpacked arrays. Using these statements will result in a warning of type ForcingEntireUnpackedArray which can promoted or demoted with the standard -error or -suppress options.

SV-LRM reference: 10.6.2

Overriding Parameters on Command Line

The -defparam NAME=value compile-time command line option can be used to override value parameter assignments in the design. Values may be any Verilog number or string constant.

Functional Coverage Improvements

Cross bin with expressions are now supported.

SV-LRM reference: 19.6.1.2

A cross coverage may involve another cross, a. k. a. cross of crosses. In previous releases, a cross of crosses was not permitted. As an extension to the SV-LRM, it is supported now with limitation: bin definitions are not permitted in a cross of crosses.

Version: 20200316.0.0

Severity Diagnostic Override

Using -override-finish-completion, an overrriding finish_number can be provided for all $finish, $stop, and $fatal statements to control the diagnostic information produced. Only 0, 1 or 2 is permitted.

SV-LRM reference: 20.10

Exported Task And Function Support With Interfaces (Experimental)

Interface Modports can now specify exported tasks and functions.

The following will result in an error being reported:

• Mismatching the prototype between the exporting instance and the modport.
• Use of an exported task or function without a corresponding export.
• Any single task or function in an interface instance being exported more than once.

Using the 'forkjoin' qualifier is not yet supported.

SV-LRM reference: 25.7.3

mintypmax Delay Mode Compile Time Options

In previous releases, the value used for a min:typ:max delay was selected at run time using -mindelays/-typdelays/-maxdelays. Although flexible, such expressions could not be used as parameters since they are not compile-time constants.

Starting with this release, options -comp-mindelays/-comp-typdelays/-comp-maxdelays have been added. These will compile in the delay selection at compile time and allow use in parameters. If these compile time options are set, the run time options will not be available for any runs against that image.

Static Lifetime Class Methods

The SV-LRM mandates that all class methods have automatic lifetime. In previous releases, any "static" lifetime methods were silently coerced to automatic. Lifetime keywords were not permitted in extern declarations or prototypes.

Starting with this release, lifetime keywords are honored for non-pure/virtual methods. Pure/virtual methods must have automatic lifetime.

SV-LRM reference: 8.6.

C Language Support

C and C++ files now listed on the command line will be compiled and linked into the image. Object files and libaries listed on the command line will be linked into the image.

Command line option '-cc compiler_name' can be used to change the compiler from the default gcc to another gcc-compatible compiler.

Command line option '-c_opts compiler_options' and 'ld_opts linker_options' can be used to append additional options to the compile and link commands.

Debugging Environment Expansion

DSim supports expansion of environment variables in filenames in various contexts.

You can now debug this process using -info ExpandEnv. DSim will print out the values of environment variables used for each expansion.

SQLite3 Database for Coverage Results

Coverage results will now be stored in an SQLite3 database by default. You no longer need to use the -write-sql command line switch to get this behaviour.

The command line switch -write-xml allows you to return to the previous behaviour of writing coverage results in XML format.

Version: 20191112.0.0

Filename Extensions

DSim can be told to interrpret custom file extensions as SystemVerilog or Verilog files using -sysvlog-ext and -vlog-ext respectively.

These can also be used in conjunction with the filename extensions used to indicate compression type.

For more details see the user manual under the sections Common Options and Input Filename Examples.

Semaphore Ordering

Prior to this release, DSim would preserve strict FIFO ordering on semaphore acquisition.

Consider a semaphore where only one key is available, and one thread is currently waiting for two keys. Another thread then attempts to obtain one key from the same semaphore.

Prior to this release, the second thread would block until two more keys were returned to the semaphore: the first key would unblock the first waiter (two keys available) and the second key would unblock the second thread.

This behavior appears to be contrary to industry standard, so it was changed. Now, the second waiter will immediately obtain the single key, and will not block. The original waiter remains blocked waiting for two keys.

Note that waiters requesting more than one key can starve under this policy.

Configurations

DSim now has limited support for libmaps and configurations. See user manual for details.

SV-LRM reference: 33.

Assertion API

VPI access to concurrent and immediate assertion objects is now supported.

Registering and removing assertion callbacks for reasons cbAssertionStart, cbAssertionSuccess, cbAssertionVacuousSuccess and cbAssertionFailure is supported.

SV-LRM reference: 39.

Simulation Runtime Messages

Messages produced during the simulation now follow the promotable/demotable convention available to compiling messages.

As documented in the User Manual messages may be promoted or demoted based on their severity and message name through the command line options.

Case Equality of Reals

DSim takes IEEE754 NaN (not-a-number) into account when comparing real nunmbers: for the relational operators defined in the SV-LRM, the result of the comparison is 1'bx if either operand is a NaN.

Strictly according to the SV-LRM, the case equality operators (=== and !==) are not valid for real numbers.

However, this treatment is not sufficient for real-number modeling (RNM). Third-party RNM libraries may use NaNs to represent special "X" and "Z" states. These libraries rely on being able to compare real numbers against the NaN constants.

As an extension to the SV-LRM, DSim now defines case equality (=== and !==) for real numbers. These operators perform a bit-for-bit comparison. Effectively, a === b is equivalent to:

 

$realtobits(a) === $realtobits(b)

 

For code intended to be portable to all simulators, it is recommended that the above style be used.

Support UVM 1.1d

DSim has added UVM 1.1d libraries for testbenches that require this specific version.

Version: 20190802.0.0

Run-Time Messages

Some run-time messages that reference a filename/line number have been enhanced to print out the "full stack" showing includes and macro expansions.

The messages printed by $finish now report the location of the $finish statement.

Users who post-process log files may need to review their scripts.

Let

The let construct is now supported, with the exception of passing event expressions as actual arguments.

SV-LRM Reference: 11.12

Functional Coverage Improvements

Set-covergroup-expressions are now supported.

SV-LRM Reference: 19.5.1.2

Coverpoint bin with expressions are now supported.

SV-LRM Reference: 19.5.1.1

Typed converpoints are now supported.

SV-LRM Reference: 19.5

SQLite3 Database for Coverage Results

Prior to this release, coverage results were written in XML format. While this is still the case, Metrics is transitioning to writing coverage results in an SQLite3 database. The database format is required to write out line and expression coverage results.

The -write-sql command line switch causes SQL format to be used instead of the XML. This mode is required to generate code coverage information.

Code Coverage

The -line-cov command line switch instruments the code for line/block coverage.

Expression Coverage

The -expr-cov command line switch instruments the code for focused expression coverage.

Toggle Coverage

The -toggle-cov command line switch enables collection of toggle coverage for variables for which callback permission (+acc+b) is enabled. Alternatively, the -toggle-cov-scope-specs command line option can be used to specify the portion of the design for which toggle coverage counts are collected.

UDP output updates are scheduled in the ACTIVE region

In past, update events for a sequential UDP output were scheduled into the NBA region. Starting from this release, these events are scheduled into the ACTIVE region in accordance with section 4.9.6 in the SV-LRM.

You may switch to the former scheduling by specifying the -seq-udp-nba-region command line option.

Soft Constraints

A new option -try-all-soft-first has been added to control soft constraint strategy.

By default, DSim will try soft constraints in order of priority to arrive at the largest prioritized subset that satisfies the constraints without contradiction. For N soft constraints, a total of N+1 solves are performed. This approach is suboptimal if the soft constraints are expected to help the solve.

With -try-all-soft-first the solver will enable all soft constraints and try a solve. If the solve succeeds then the resulting solution is used. Otherwise, the solver reverts to the regular behavior of trying soft constraints one by one.

Default error message promotion/demotion

The -error/warn/info/suppress options now accept "error", "warning" and "note" as arguments, which serve to promote/demote all messages of a given class.

e.g. -error warning turns all warnings into errors.

If both a message-specific override and a general override are given, then the specific override takes precedence.

e.g. -error MultiBlockWrite -suppress warning

turns off all warnings, with the exception of "MultiBlockWrite", which becomes an error.

It is not possible to demote errors or fatal errors.

Random Number Generator Seeding

The argument to -sv_seed is now treated as an arbitrary-width hexadecimal constant. Since the RNG has 1024 bits of state you can now provide 1024 bits of external entropy. Previously you could provide only 32 bits, as the argument was interpreted as an integer constant.

Since the seeding algorithm has also changed, all tests that use randomization will now produce different results.

In addition, it was found that the RNG used by $random and $dist_... functions did not conform to the SV-LRM. This has been fixed.

DPI library tracing

A new option -trace-dpi has been added, to print positive confirmation of DPI library loading.

Sign-extension and port connections

The SV-LRM states that port connections for input and output ports are made using continuous assignments.

However, the SV-LRM also permits net collapsing to be performed.

If the formal and actual for a port connection differ in width and a continuous assignment is used then either zero-extension or sign-extension ought to be performed using standard expression evaluation rules. However, the situation is not so clear if net collapsing is being performed. Performing any type of extension will result in shorting wires together.

DSim will use a continuous assignment (and perform required extension) if either the formal or actual is a variable. DSim will not perform extension if both sides of a port connection are nets, so that net collapsing can be performed.

SV-LRM Reference: 10.7, 23.3.3

Deferred immediate assertions

The deferred assertion statements assert #0, assume #0, cover #0, assert final, assume final, and cover final are now supported.

SV-LRM Reference: 16.4

Property Operators

Support for the following property operators has been added: eventually, s_eventually, nexttime, s_nexttime, until, s_until, until_with, s_until_with, always, s_always

SV-LRM Reference: 16.12

Version: 20190115.0.0

Deprecated SDF prepare options

The -sdf-int-prepare and -sdf-device-prepare command line options have been removed. The simulator will now determine which constructs may have SDF interconnect type constructs automatically.

These options should be removed from configuration scripts.

Specification of attributes on per-item basis

DSim now supports specification of certain properties on a per-item basis:

• -acc-specs for specifying VPI access to variables and paths
• -timingcheck-specs for specifying timing checks to enable/ignore
• -wave-scope-specs for selecting signals to dump on command line

See user manual for details.

$deposit(signal, value)

This system call is similar to a force statement: it sets the specified signal to a certain value, but unlike force does not need to be released. The value is used to simulate the signal until a new value is assigned. The assignment takes effect immediately with the highest precedence, it will override a procedural force or assign.

The value is released when another update of the signal occurs through regular processing of the simulation.

The signal can be a variable/net, or an expression on a variable/net, such as an array reference or slice, indicating where to put the value. The value's should match the signal expression's type.

SV-LRM Deviation/Extension: commonly supported by simulators

Procedural Force Enhancement

The types of variables/nets that can be forced has been enhanced to support:

• Forcing of individually indexed bits or part selects of a variable (or net, however nets were previously supported)
• Forcing of individually indexed singular elements of an unpacked array (variable or net)
• Forcing of singular elements of unpacked structs is still unsupported.

There are restrictions on the operations that can be done with forced variables. Please see the Known Issues document for details

SV-LRM Reference: 10.6.2

Net Alias

Net aliasing is now supported

SV-LRM Reference: 10.11

SystemVerilog Assertions

Support has been added for multiclocked sequences and properties.

SV-LRM Reference: 16

Version: 20180705.0.0

Interface Classes

DSim now supports interface classes.

SV-LRM Reference: 8.26

Case Inside

DSim now supports case (...) inside

SV-LRM Reference: 12.5.4

Delay Modes

DSim now supports 4 delay modes: delay_mode_zero, delay_mode_unit, delay_mode_distributed, and delay_mode_path. The user may specify the delay mode through command line options and/or compiler directives. Note that the respective command line options are mutually exclusive. The command line option acts as if it is the first compiler directive in the topmost source file. A subsequent delay mode directive supersedes the current one.

zero

command line option: +delay_mode_zero compiler directive : `delay_mode_zero

This delay mode removes distributed delays, specify path delays and timing checks.

unit

command line option: +delay_mode_unit compiler directive : `delay_mode_unit

This delay mode changes non-zero distributed delays to 1 precision time unit. It also disables specify path delays and timing checks.

distributed

command line option: +delay_mode_distributed compiler directive : `delay_mode_distributed

This delay mode disables and removes all path delays in favour of distributed delays.

path

command line option: +delay_mode_path compiler directive : `delay_mode_path

This delay mode sets all distributed delays to 0 and uses only path delays.

SV-LRM Reference: E.4 E.5 E.6 E.7

SystemVerilog Assertions

Support has been added for the sequence operator properties weak and strong and immediate assume statements.

SV-LRM Reference: 16

Version: 20180406.0.0

Assignment Pattern vs. Empty Queue

An "empty" assignment pattern '{} is now accepted as an empty queue, to accommodate legacy code.

SV-LRM Reference: 10.9

Aggressive Optimizations

The dead block removal optimization has been made more aggressive, and will now remove items that would otherwise show up on a waveform dump. The best setting to retain items for a waveform dump is +acc+b.

Tran Solver Improvements

Improvements have been made to the tran solver, which may result in a speedup in certain applications.

Timing Checks

All timing checks are now supported including negative timing checks.

Timing checks, including negative timing checks, are on by default.

New command line options include:

• +/-notimingchecks - compile option - Turn off timing checks
• +/-nonegtchk - compile option - Turn off negative timing check limits by setting negatives to 0
• +/-ntcnotchk - compile option - Turn off timing checks but do calculate delayed signals wrt NTC
• +/-nonotifier - runtime option - Turn off timing check notifier toggling
• +/-no_tchk_msg - runtime option - Turn off timing check violation messages, notifier still toggles
• -tchk_msg_start time - runtime option (default time=1) to start reporting violations no earlier than time. Note that the timing checks are always evaluated prior to the time, but violation reports are suppressed.

SV-LRM Reference: 31

Backannotation using the standard delay format (SDF)

SDF annotation of module path delays, interconnect delays, and timing checks is now supported.

SDF annotation is on by default and is activated with the $sdf_annotate call.

New command line options include:

• +/-nosdf - runtime option - Turns off sdf annotation
• -sdf-int-prepare <path> - compile option - Prepare instances within path for SDF INTERCONNECT, PORT, and NETDELAY overrides
• -sdf-device-prepare <path> - compile option - Prepare primitives within path for SDF DEVICE overrides
• +multisource_int_delays - runtime option - Turns on interconnect multisource and pulse handling with SDF annotation
• -sdf-verbose - runtime option - Log SDF annotation information about all errors

SV-LRM Reference: 32

SystemVerilog 2017

The -sv2017 keyword has been added. This is a synonym for -sv2012 as no new keywords have been added to the language.

Support for:

 

`begin_keywords "1800-2017"

 

has also been added.

Version and version verbose

The DSim version is now entered in the simulation run log. That can be used to check the exact version of DSim that was in use for that run. There are 2 command line options to check the version:

• -version - prints the proper released name of DSim
• -version-verbose - prints extra information about the build and the release was built from. This will match the version printed into the log file.

Delay Mode Zero

For the purposes of functional testing without timing, in the most runtime efficient way, delay mode zero has been implemented as a command line option:

• +delay_mode_zero - Compile time option that removes distributed delays, specify path delays and timing checks

Consider running the simulation with +nosdf whenever +delay_mode_zero is used because SDF constructs referencing delays and timing checks removed by this option will result in errors in the sdf log.

Version: 20180213.0.0

SystemVerilog Assertions

Support has been added for the case property, default actual arguments, $asserton, $assertoff, $assertkill, and immediate cover statements.

SV-LRM Reference: 16

Coverage of Enumeration Bins

The coverage option auto_bin_max is specified in the SV-LRM to limit the number of automatic bins created for a coverpoint, but is specifically not applicable to bins of enumeration type. The option -limit-enum-bins has been added to override the SV-LRM compliant behavior, and to subject bins of enumerated type to the same limit.

SV-LRM Reference: 19.5.3

Interconnect Type

Preliminary support has been added for generic interconnect. This should be considered an alpha feature.

SV-LRM Reference: 6.6.8

Version: 20171115.0.0

Elaboration Enhancements

Description:

The elaborator has been completely reworked for this release. The following features are now supported:

• Use of structs and struct members in parameters
• Use of enumerations in parameters
• Connection of a formal interface port to an actual interface that may involve a parameter specialization and/or a modport. Previously, the type of the formal and actual and to match exactly, with identical parameterization and modport use. Coercion of the formal is now performed as required. This coercion is not formally defined in the SV-LRM, but appears to be industry standard.

SystemVerilog Assertions

Description:

The subset of supported SystemVerilog Concurrent Assertions has been enlarged. All concurrent assertion statements, both static and in procedural code, are supported. All sequence operators are supported, including sequence instantiations. The subset of available property operators is: |->, |=>, not, #-#, #=#, and, or, if/else, iff, implies . Use of any other property operator is flagged as an error.

Sequence events, and the sequence method .triggered are supported, both in concurrent assertions and in procedural code.

Only singly clocked assertions are supported. Use of multi-clocked sequences or properties is flagged as an error.

The expect property statement is not supported.

The -no-sva command-line option disables SVA support, causing the following items to be ignored during compilation:

• any concurrent assertion statement
• property or sequence declaration
• expect property statement

SV-LRM Reference: 16

Version: 20170915.0.0

Specify Blocks

Description:

Dsim now supports timing specified in module specify blocks.

The following command line options have been added to control the behaviour; please see the user manual for details:

• -pathpulse
• +transport_path_delay
• -pulse_e
• -pulse_r
• -pulse_e-onevent
• -pulse_e-ondetect
• -noshowcancelled
• -showcancelled
• -pulse_e-no-cancelled-msg
• -pulse_e-no-warn-msg
• -nospecify
• -specify
• -specify-zero
• -specify-unit

SV-LRM Reference: 30

User-Defined Nettypes

DSim has experimental support for user-defined nettypes.

SV-LRM Reference: 6.6.7

SystemVerilog Assertions

Description:

The subset of supported SystemVerilog Concurrent Assertions has been enlarged. Both assert property and cover property assertion statements are supported outside procedural code. All sequence operators are supported, including sequence instantiations. However, only a limited subset of property operators is available: |->, |=>, not, #-#, #=#. Use of any other property operator is flagged as an error.

Sequence events, and the sequence method .triggered are supported, both in concurrent assertions and in procedural code.

Only singly clocked assertions are supported. Use of multi-clocked sequences or properties is flagged as an error.

The following statements are ignored: procedural assert property, procedural cover property, cover sequence, assume property, restrict property.

The -no-sva command-line option disables SVA support, causing the following items to be ignored during compilation:

• any concurrent assertion statement
• property or sequence declaration
• expect property statement

SV-LRM Reference: 16

Creating Default Class Specializations

By default, specializations of a parameterized class are created only if they are referenced by other code. However, the following coding style will cause a problem:

 

class my_test#(parameter FOO=2) extends uvm_test;
`uvm_component_utils(my_test)
...
endclass

 

This class was not intended to be treated as a paremterized class; localparam should have been used instead of parameter. As given, however, due to the parameter, no specializations will be created, since this class is not explicitly instantiated by any code. UVM uses a static initializer to create an instance and register the test with the factory, but this won't happen.

The switch -all-class-spec is used to work around this problem. When given, default specializations will be created for classes that have only value parameters (no type parameters), and which have a static initializer.

Delays on Hierarchical Path

Fixed a bug which caused a crash when a hierarchical path was used in a continuous assignment or gate output which had a delay specified.

UDP optimization

Optimizations were done which minimize UDP signal sensitivity and allow the grouping of UDP instances with common sensitivities allowing for significant runtime improvements where applicable. This optimization is only applicable with the UDP instances do not have strength or delays.

Version: 20170529.0.0

SV language support

Description:

IEEE Std 1800-2012 set of reserved keywords is now the default set of keywords for all files except *.v files. Previously, it was the IEEE Std 1800-2009 set of reserved keywords.

The IEEE Std 1800-2012 set of reserved keywords has identifiers that are not present in the IEEE Std 1800-2009 set of reserved keywords. In prior releases, the -sv2012 option was needed to enable recognition of these identifiers as keywords, e. g. "soft". In the current release, this is no longer required. However, -sv2009 may be required for legacy code where these identifiers are used to give an object a unique name.

SV-LRM Reference: Table 22-6

VPI support

Description:

DSim now has support for a subset of VPI, which permits UVM backdoor register accesses to variables (not nets). This feature should be considered experimental.

SV-LRM Reference: 37/38

Dead method / gate optimizations

Description:

DSim will now refrain from generating code for tasks/functions that are provably never called. This may substantially reduce the amount of code generated for large UVM testbenches.

DSim will now remove gate and UDP instances from library cells marked with `celldefine if their output is provably unused. This can happen if the output is used only for specify conditions or timing checks, which are currently not supported.

Combinational glitch removal

Description:

RTL code often uses a coding style intended to avoid inadvertent latch inference:

 

always @* begin
    x = 0;
    y = 0;
    if (a) x = 1;
    if (b) y = 1;
end

 

In the event that b rises while a is already high, a glitch will be created on x as it is set to 0 and then immediately set to 1. Strictly according to the SV-LRM this glitch must be produced, as other processes may be sensitive to it. However, it is possible to code simulation logic loops by creating two blocks sensitive to each other's glitches. This style may not result in an actual combinational loop during synthesis, and it may not cause a simulation loop on other simulators, depending on how the tools optimize and schedule the processes.

For the benefit of users migrating from other tools with legacy code that causes a simulation loop due to this coding style, the option -opt-comb-glitch will enable a transform that suppresses some of these glitches. The resulting simulation will not be SV-LRM compliant, and may break conformant code, but it may also allow non-conforming legacy code to simulate properly.

SV-LRM Reference: 4.9.3 second paragraph, in the case where no delay is specified.

Version: 20170418.0.0

+ignore+directive1+...+directiveN

Description: A mechanism is included for specifying non-standard compiler directives which appear in the SystemVerilog source for use by various tools, but which are not supported by DSim. To engage this mechanism, all non-standard compiler directives shall be listed in +ignore option:

+ignore+directive1+...+directiveN

Note that this this mechanism doesn't affect the substitution of macros. For example:

 

\`define directive1 something

\`directive1

 

'directive1' is substituted by 'something' even if it appears in ignore option.

SV-LRM Reference: N/A

$countdrivers

Description:

The optional system task $countdrivers is now available. Drivers with value 1'bz are electrically isolated from a net, therefore, they are not considered for the purpose of counting drivers on the net.

SV-LRM Reference: D.2

Local Parallel Compile

Description:

The -j N option can be used to specify the mumber of threads used during compilation. Default is 1. Care should be taken to ensure that the compile machine has sufficient resources (both CPU cores and RAM) to handle all concurrent compile jobs.

Constraint Solver Improvements

Description:

A number of improvements have been made to the constraint solver which can reduce solving time considerably on certain problems.

Version: 20170315.0.0

SystemVerilog Assertions

Description:

The experimental command line switch -sva will turn on partial support for SystemVerilog Assertions. Only property assert statements in non-procedural code are currently supported.

This feature is still in alpha development, and is not yet ready to be used.

SV-LRM Reference: 16

Performance optimization

Description:

Significant improvements have been made to runtime performance, up to 2x faster for some testbenches.

Soft Constraints

Description:

Soft constraints are now supported. Soft constraints are a SystemVerilog 2012 feature; they must be enabled with -sv2012.

SV-LRM Reference: 18.5.14

Randomize in Constructor

DSim now permits randomize() calls inside constructors. Note that this is dangerous: if a constraint is overridden in a subclass, then randomization will happen considering constraints for a class instance that is not fully constructed. This scenario is not defined in the SV-LRM.

Assignment Between Strings and Integral Types

DSim will now permit assignments between SystemVerilog strings and integral types if the -allow-string-int-assign option is given. This is potentially dangerous as e.g. type mismatches between task/function formals and actuals will go undetected.

e.g.:

 

int x;
string s;

s = string'(x); // always legal
x = int'(s); // always legal
x = s[0]; // always legal, as s[0] is a byte
x = s; // Allowed only with -allow-string-int-assign
s = x; // Allowed only with -allow-string-int-assign

 

---

Version: 20170113.0.0

User-defined Primitives

Description:

User-defined primitives are now supported as described in the SV-LRM with no known deficiencies.

SV-LRM Reference: 29

Strength Propagation - Net and Port collapsing

Description:

When a net carrying a strength specification other than strong passes through a port the strength will be preserved on the other side of the port where the expressions on both sides of the port are structural net expressions. The nets will be combined in accordance with the rules in SV-LRM section 23.3.3.7.

SV-LRM Reference: 23.3.3.7

Library Support Command Line Options

Description:

-v filename.v

Sets filename.v to be a library file to search for modules. If a design element is not resolved, then library files can be analyzed to find it. Multiple design elements may be present in a single library file.

-y libdir <+libext+suffix>

Set libdir to be a library directory to search for modules. If a design element my_module is not resolved, the libdir will be searched for a file with the name my_module and that file is opened and analyzed to find the my_module definition. One or more suffixes can be specified with the option +libext+suffix1+suffix2…

SV-LRM Reference: n/a

Optimizations

Description:

Some more RTL code optimizations have been implemented, yielding compile and run time improvements compared to the previous release.

Some changes have been made to the scheduler, which also improves performance.

SV-LRM Reference: n/a

Constant Functions

Description:

Constant functions have been implemented. Under certain conditions, it is legal to call functions from a constant expression; these functions are interpreted at compile time to yield a constant return value.

SV-LRM Reference: 13.4.3

Calling Tasks from Functions

Description:

Some support has been added for calling tasks from functions. Called tasks cannot contain blocking statements, nor can they contain disable statements. If the called task is a virtual class method, then these restrictions apply to all overrides in any subclasses. Tasks that meet these requirements can be called as if they were functions.

DSim will also analyze tasks calls from tasks, and will call them as if they were functions if permissible. Calling a task "directly" rather than scheduling it yields a small performance improvement.

SV-LRM Reference: n/a

Gate Modelling with Net & Gate Delays

Description:

DSim now fully supports gate/switch level modeling (including tran), net and gate delays.

SV-LRM Reference: 28

P1735 Encryption Support

Description:

DSim supports IEEE1735 IP protection at the V1 compliance level. IP vendors should contact Metrics Design Automation Inc for the public key.

SV-LRM Reference: n/a

Specify Parameters

Description:

DSim now supports specparam declarations.

SV-LRM Reference: 60.20.5