User Guide: DSim Stages Of A Simulation

Running a simulation in DSim is done in three distinct stages

Analyze (Compile): This is the process in which each design file is parsed and interpreted based on the particular language syntax. The resulting design components are saved for elaboration. Any syntax-related or other problems with the files are reported here.

Elaborate: Based on the desired top-level component(s) of a design, all other required components are taken and resolved into a final design image which is saved to disk. Any resolution issues (ie. missing components, incompatible references, etc..) are reported here.

Run: The final image is loaded by DSim, initialized and executed. The simulation will proceed until completion or a problem occurs. Non-static warnings and errors which can only be detected during the execution of the simulation are reported here.

The DSim tools allows users various control through the three stages if needed.

Example: Hello World

Using the following simple example we will look at all the different ways the Analyze, Elaborate, and Run can be combined to execute the design. This little design can be processed in a variety of ways by combining the stages or doing them one by one. In general, there can be a significant overall performance improvement if you analyze/elaborate once and run multiple times maybe with different tests or various seed values.

Given the simple SystemVerilog design, hello.sv:

module top;
    initial
    begin
        $display ("%t Hello World", $time);
    end
endmodule

3-Step Approach

Analyze (or Compile): (note for VHDL you would use dvhcom instead of dvlcom)

dvlcom hello.sv -lib myLib

Elaborate: specifying the previously analyzed library and the name of the desired output image

dsim -genimage myImage -top myLib.top -lib myLib

Run (or Simulate): specify the previously generated image

dsim -image myImage

2-Step Approach

There are 2 ways to combine the stages to make a 2-step approach. Both are supported for SystemVerilog/Verilog but for VHDL, the Analyze stage must always be its own step.

2-Step Approach:: Analyze+Elaborate then Run

(ONLY available for SystemVerilog/Verilog)

Analyze+Elaborate:

dsim -genimage myImage

Run:

dsim -image myImage

2-Step Approach:: Analyze then Elaborate+Run

Analyze : (note for VHDL you would use dvhcom instead of dvlcom)

dvlcom hello.sv -lib myLib

Elaborate+Run

dsim -top myLib.top -lib myLib

1-Step Approach

Only available for SystemVerilog/Verilog this approach does all 3 stages with one command:

dsim hello.sv