How To: Simulate Mixed Language Designs
DSim fully supports mixed language designs in VHDL, Verilog, and SystemVerilog. There are different methods to compile and run your design, depending on the following:
- if VHDL is used, or the design is purely Verilog / SystemVerilog
- you want to compile once, run multiple times
- your preference for the 3 stages of simulation (Analyze (Compile), Elaborate, Run)
Commands
dvhcom
is required to compile any VHDL filesdvlcom
is used to compile any Verilog / SystemVerilog filesdsim -a '-genimage ...'
is used to elaborate the design after the files have been compileddsim -a '-image ...'
is used to run the image after the design has been elaborateddsim -a '-F filelist.txt ...'
is used to compile, elaborate, and run designs that are purely Verilog / SystemVerilog
Methods
1. 1-step Method: Compile, Elaborate, and Run in one step.
This method is applicable if both are true:
- the design is purely Verilog / SystemVerilog
- you want to compile everything on every run (compile once, run once)
2. 2-step Method: Compile and Elaborate in one step, Run in a second step.
This method is applicable if both are true:
- the design is purely Verilog / SystemVerilog
- you want to compile once, run multiple times
3. 3-step Method: Compile, Elaborate and Run in 3 separate steps.
This method is applicable if either are true:
- the design has VHDL and Verilog / SystemVerilog
- you want to compile once, run multiple times
To learn how to use these methods, go to the appropriate section for your tool.
DSim Studio
Watch this video.
DSim
1-step Method: Compile, Elaborate, and Run in one step.
Command:
dsim <design files> <options>
Examples:
dsim -F filelist.txt +acc+b -waves waves.mxd dsim my_dut.v my_ip.v my_tb.sv -timescale 1ns/1ps +acc+b -waves waves.mxd
2-step Method: Compile and Elaborate in one step, Run in a second step.
Commands:
dsim -genimage <image> <design files> <elaboration options> dsim -image <image> <run options>
Example:
dsim -genimage myimage -F filelist.txt +acc+b dsim -image myimage -waves waves.mxd
3-step Method: Compile, Elaborate and Run in 3 separate steps.
Commands:
dvhcom <vhdl design files> dvlcom <verilog or SystemVerilog files> dsim -genimage <image> -top <library>.<module> <elaboration options> dsim -image <image> <run options>
Example:
dvhcom -F filelist_VHDL.txt dvlcom -F filelist_SV.txt dsim -genimage myimage -top work.carry_lookahead_adder_tb +acc+b dsim -image myimage -waves waves.mxd
DSim Cloud
1-step Method: Compile, Elaborate, and Run in one step.
Command:
mdc dsim -a '<design files> <options>'
Examples:
mdc dsim -a '-F filelist.txt +acc+b -waves waves.mxd' mdc dsim -a 'my_dut.v my_ip.v my_tb.sv -timescale 1ns/1ps +acc+b -waves waves.mxd'
2-step Method: Compile and Elaborate in one step, Run in a second step.
Commands:
mdc dsim -a '-genimage <image> <design files> <elaboration options>' mdc dsim -a '-image <image> <run options>'
Example:
mdc dsim -a '-genimage myimage -F filelist.txt +acc+b' mdc dsim -a '-image myimage -waves waves.mxd'
3-step Method: Compile, Elaborate and Run in 3 separate steps.
Commands:
mdc dvhcom -a '<vhdl design files>' mdc dvlcom -a '<verilog or SystemVerilog files>' mdc dsim -a '-genimage <image> -top <library>.<module> <elaboration options>' mdc dsim -a '-image <image> <run options>'
Example:
mdc dvhcom -a '-F filelist_VHDL.txt' mdc dvlcom -a '-F filelist_SV.txt' mdc dsim -a '-genimage myimage -top work.carry_lookahead_adder_tb +acc+b' mdc dsim -a '-image myimage -waves waves.mxd'
Example
The carry_lookahead_adder example from the Walkthrough Tutorial has folders for VHDL, SystemVerilog, and VHDL_SystemVerilog implementations of the same design. Open /sim/readme.txt under these folders to see how to simulate the design according to the language(s) and methods described above.
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