Things to Watch Out for When Simulating

Modified on Tue, 9 Jul at 6:07 PM

Things to Watch Out for When Simulating

1. I deleted my .mdc folder before destroying the remote workspace.

If you cannot recover your .mdc folder to destroy the remote workspace through the DSim Cloud CLI (mdc), you can destroy the remote workspace through the DSim Cloud Portal Interactive Workspaces menu.



2. My design passes Analysis, but fails Elaboration.

If all of your design files Analyze successfully but do not Elaborate successfully, you may get these types of errors:


 

=E:[UnresolvedModule]:  
Unable to find definitions for the following

 


 

=E:[UndefIdentifier]:
Undefined identifiers:

 


 

=E:[InvalidAggNames]:  
The following named choices were not recognized:

 

These errors are typically caused by missing libraries or dependencies. Ensure that all such libraries and dependencies have been properly analyzed and referenced. If the libraries are vendor or third-party, ensure they are included in your local workspace. If they are encrypted, ensure they have been encrypted with the Metrics public key. If they are the standard Intel Quartus or Xilinx Vivado libraries, you can use the respective precompiled libraries provided by DSim Cloud.



3. My UVM design is missing UVM library components.

You may get these types of errors during Elaboration of UVM designs:


 

=E:[UndefIdentifier]:  
Undefined identifiers:

 


 

=E:[IncNotFound]:  
The following include files were not found in the include search path:  
<path to file referencing uvm header file> uvm_macros.svh

 


 

=E:[ForwardPkg]:  
A package cannot be imported or referenced before it is defined:  
<path to file referencing uvm library package> uvm_pkg

 

The Universal Verification Methodology (UVM) library is supplied by Metrics and is made available to users on-demand in the remote workspace. To use it, you must include uvm_macros.svh and import the UVM package in all your design files that require them. Then you must compile the UVM package and load the UVM DPI library.


See How To: Use UVM in a Simulation to perform these steps.



4. My simulation has hung!

See How To: Debug a Hung Simulation.



5. Can I compile C/C++ code with my simulation?

Yes you can! See How To: Integrate C/C++ Files with Your Design.



6. Can I simulate mixed language designs?

Yes you can! See How To: Simulate Mixed Language Designs.



7. I get a Remote exited with out of memory error. What do I do?

Start a new remote workspace with the s8 remote cloud compute configuration and try simulating again:


 

mdc workspace start --size s8

 

See DSim Cloud CLI Tool remote cloud compute configuration for details.



8. How do I suppress or filter compilation messages?

Simply Tune DSim Messaging.



9. How do I see what Regression jobs are running and their IDs?

Simply use mdc job list.



10. How do I view my simulation waveforms?

Simply use view wave in Interactive mode, or job wave in Job mode.



11. Why does the output streamed to my terminal appear out of order?

The output streamed to your terminal is a combination of the streams from stdout and stderr. These streams are processed by DSim Cloud to direct them to their intended destination. In Interactive mode, they are streamed across the internet to your terminal. In Job mode, they are streamed to a file. This processing results in the two independent streams having slight delay. Hence the lines may appear out of order in your terminal, though they are correct in the remote workspace.


To view the output with the correct order, simply download the DSim log files (dsim.log, dvlcom.log, dvhcom.log) using mdc download in Interactive mode, or using mdc job download in Job mode.


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