How To: Set up Intel Quartus Precompiled Libraries in DSim Cloud
DSim Cloud comes with the Intel Quartus standard libraries, both Verilog and VHDL, precompiled. The following are the precompiled standard libraries:
- altera
- altera_ver
- altera_lnsim
- altera_lnsim_ver
- altera_mf
- altera_mf_ver
- lpm
- lpm_ver
- sgate
- sgate_ver
Procedure
To use the Quartus precompiled libraries in your DSim simulations, you need to map them as follows:
1. In a local workspace with an active remote workspace, modify and save the configuration file mdc_config.yml for the appropriate VHDL library. To see how to change your mdc_config.yml, see DSim Cloud Configuration.
2a. To map the Quartus libraries with the VHDL IEEE-1993 library, uncomment the entry for the Quartus package in your mdc_config.yml:
- name: quartus version: "22.2"
2b. To map the Quartus libraries with the VHDL IEEE-2008 library, change the version field of the IEEE library to "08" and uncomment the entry for the Quartus package in your mdc_config.yml:
- name: ieee version: "08" - name: quartus version: "22.2"
3. For every Verilog library component required in your design, ensure to add it to your DSim command:
dsim -L <lib_ver>
For example:
mdc dsim -a '-F filelist.txt -L altera_ver -L lpm_ver -L sgate_ver +acc+b -waves waves.mxd'
Optional
To see what libraries are mapped in your work directory, enter:
mdc dlib -a 'ls'
To see the components inside a particular library, like mylib, enter:
mdc dlib -a 'ls -lib mylib'
Example
You can try out the above Procedure with a provided example design as follows:
1. Download example_quartus-main.zip.
2. Extract the contents of this file into a folder called example_quartus-main.
3. Open a terminal window and navigate to example_quartus-main:
cd example_quartus-main
4. Start a DSim Cloud Interactive workspace:
mdc initialize --local-only mdc workspace start
5. Navigate to SystemVerilog/sim:
cd SystemVerilog/sim
6. Compile and run the simulation:
mdc dsim -a '-F filelist.txt -L lpm_ver +acc+b -waves waves.mxd'
To get a better understanding of how to use DSim Cloud for mixed language simulations, open readme.txt under the /sim folder of the appropriate language (SystemVerilog / VHDL / VHDL_SystemVerilog).
See also
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