Tutorial: DSim Desktop for Intel

Contents

1. Introduction
2. Prerequisites
3. Example design
4. Open a project
5. Create a project
6. Add files to your project
7. Add a Simulation Configuration
8. Compile your design
9. Run your design
10. View the waveform
11. Debug your design
12. Run your design in the cloud
13. Next Steps

Introduction

DSim Desktop is a versatile Visual Studio Code (VSC) extension, offering unparalleled flexibility in HDL simulation, supporting both cloud-based and local (on-prem) workflows. This article describes how to use DSim Desktop to simulate the Intel Quartus Reference Design "Turbo-V".

NOTE: The screenshots in this article may not exactly match what you see on your computer. The functionality and performance of DSim Desktop remain the same.

Prerequisites

Quartus

1. Have a working installation of Quartus Prime 22.2 Standard or Pro on your local machine.
2. Install Intel® Arria® 10 device support.
3. Set the Windows System environment variables QUARTUS_HOME = <path to Quartus installation>/<version>/quartus and IP_HOME = <path to Quartus installation>/<version>/ip.

DSim Desktop

1. Install DSim Desktop.
2. Tour of DSim Desktop.

Example design

For this tutorial, use the intel_FPGA_turbov_0_example_design example design. If you haven't already done so,

1. Generate the Intel Quartus Reference Design "Turbo-V". You do not have to Simulate the "Turbo-V" design with DSim Cloud.

2. Download and extract the contents of metrics-sim-turbov-main.zip.

3. Copy the file mdc_config.yml into the project folder /turbo_v/intel_FPGA_turbov_0_example_design/ and the folder /metrics into /turbo_v/intel_FPGA_turbov_0_example_design/simulation_scripts/.

4. Click the VSC Explorer and navigate to the folder /intel_FPGA_turbov_0_example_design. If the folder is not visible in the VSC Explorer, open it by clicking Open Folder from the File menu.

If you want to simply compile and simulate this example design, proceed to Open a project.

If you want to create the project from scratch, proceed to Create a project.

Open a project

To open an existing project, simply right-click the project's .dpf file from the VSC Explorer and select DSim Desktop: Open Project.

For this tutorial, navigate to the folder /simulation_scripts/metrics, right-click turbov_tutorial.dpf and select DSim Desktop: Open Project.

Then skip to the step Compile your design.

Create a project

Simulating designs in DSim Desktop is project-based, so the first thing you need to do is create a project.

1. Navigate to the folder /simulation_scripts, right-click the folder /metrics and select DSim Desktop: New Project.

2. Enter turbov for the Project File Name, ..\.. for the Design Root Directory, work for the Working Directory, and click Save.

Add files to your project

As with any simulator, you need to know all the source files and their dependent files that need to be compiled, as well as what libraries they are compiled into. It is highly recommended that you use file lists to compile files of the same language and options.

Example steps

1. Navigate to /simulation_scripts/metrics/common, right-click altera_filelist.txt and select DSim Desktop: Configure File.

2. This is a file list of VHDL files to be compiled into the library altera, so enter altera into the box Library Name (Optional), select VHDL from Choose a Language, and tick the box Configure as file list. Click Save.

3. Navigate to /src, right-click intel_FPGA_turbov_0_example_design_core.v and select DSim Desktop: Configure File.

4. This is a Verilog file to be compiled into the default library work, so the defaults are correct. Click Save.

5. Add the rest of the files to your project using one of the following methods (a or b):

a) Load the pre-populated project file turbov_no_sim.dpf by right-clicking the file and selecting DSim Desktop: Open Project.

b) Similar to the previous steps, add the following files or file lists (.txt) to your project to the proper libraries in the following order. All files and file lists are under /simulation_scripts/metrics/common/*.

File or File List	Language	Library	Options	Order
altera_lnsim_filelist.txt	VHDL	altera_lnsim		1
altera_mf_filelist.txt	VHDL	altera_mf		2
lpm_filelist.txt	VHDL	lpm		3
sgate_filelist.txt	VHDL	sgate		4
altera_ver_filelist.txt	Verilog	altera_ver		5
altera_lnsim_ver_filelist.txt	Verilog	altera_lnsim_ver		6
altera_mf_ver_filelist.txt	Verilog	altera_mf_ver		7
lpm_ver_filelist.txt	Verilog	lpm_ver		8
sgate_ver_filelist.txt	Verilog	sgate_ver		9
twentynm_hip_filelist.txt	VHDL	twentynm_hip		10
twentynm_hssi_filelist.txt	VHDL	twentynm_hssi		11
work_vhdl93_filelist.txt	VHDL	work		12
twentynm_ver_filelist.txt	Verilog	twentynm_ver		13
twentynm_hip_ver_filelist.txt	Verilog	twentynm_hip_ver		14
twentynm_hssi_ver_filelist.txt	Verilog	twentynm_hssi_ver		15
work_verilog_filelist.txt	Verilog	work		16
work_sv_filelist.txt	SystemVerilog	work	-sv	18

• In the LIBRARY CONFIGURATION view, expand the library work and right-click ....\src\intel_FPGA_turbov_0_example_design_core.v. Select Change Order.

• Enter 17 for the position (compile order) and press <Enter>.

6. Click the DSim Desktop view and expand the libraries in the LIBRARY CONFIGURATION.

7. Confirm that all your libraries match the ones above and expand the library work (Verilog/SystemVerilog) to verify the order of the last 3 files. Note that there are different icons for file lists and files. The ? beside the libraries and files indicate that their Compilation Status is Unknown, ie. they have not been compiled yet.

Add a Simulation Configuration

Once you've finished adding all of your files to your project, you can add a Simulation Configuration. This enables you to elaborate and run different simulations on the same set of compiled libraries. Add a new Simulation Configuration:

1. Hover over the SIMULATION CONFIGURATION drop-down menu and click the + button.

2. Enter the following in the Configure Simulation tab:

• Sim 1 for the Simulation Name.
• -top work.turbov_ul_top_tb -libmap ..\common\lib.map -timescale 1ps/1ps +acc+b -waves waves.mxd -suppress NumericStd:ArraySubtypeWarning for the Options. These are the DSim options executed when you hit the 'Run' button. In our example, this elaborates and runs the testbench as the top-level module and generates a waveform file during runtime as specified by the Options:

-top work.turbov_ul_top_tb: top-level module is turbov_ul_top_tb found in the compiled library work

-libmap ..\common\lib.map: specify lib.map as the library mapping file

-timescale 1ps/1ps: set the default timescale to 1ps/1ps

+acc+b: generate support for waveform dump

-waves waves.mxd: enable wave dump to waves.mxd

-suppress NumericStd:ArraySubtypeWarning: suppress emission of the NumericStd:ArraySubtypeWarning message

Click Save.

For common DSim options, see the DSim column under the Standard Options section of DSim Common Options.

Compile your design

1. Click the 'Compile Project' play button under the LIBRARY CONFIGURATION to compile your project.

All of the executed DSim simulator commands and their resulting output are displayed in the OUTPUT window. A notification pops up indicating the overall result of the compile. The ? beside the libraries in the LIBRARY CONFIGURATION turn into check marks after the successful compilation of the library.

Optionally, click the 'Turn Auto Scrolling On' button (lock icon) in the OUTPUT window to have the output scroll automatically.

Run your design

After the successful compilation of your design, you can run it locally (on-prem) by simply clicking the 'Run' button beside Sim 1 in the SIMULATION CONFIGURATION.

All of the executed DSim simulator commands and their resulting output are displayed in the OUTPUT window. A notification pops up indicating the overall result of the run. A check mark appears beside Sim 1 in the SIMULATION CONFIGURATION after a completed simulation run.

View the waveform

1. Click the VSC Explorer and double-click on /simulation_scripts/metrics/work/waves.mxd.

2. Use the integrated waveform viewer like you would any other waveform viewer. See User Guide: Metrics Waveform Viewer for details.

3. Close the waves.mxd tab when you're done. Subsequent simulations will overwrite this waveform file unless you change its name in the Simulation Configuration Options dialog box.

Debug your design

1. Using a combination of the waveform waves.mxd, the compilation log dvlcom.log, and the simulation log dsim.log, debug your design.

2. Make any necessary changes to your HDL and testbench files in the VSC Explorer and save them.

3. Close all the tabs in the Editor pane.

4. You only need to re-compile the files or libraries that have changed. For example, if you only changed the testbench file, click the 'Compile File' play button next to work_sv_filelist.txt (since turbov_ul_top_tb.sv is part of this file list) in the LIBRARY CONFIGURATION of the DSim Desktop view.

5. After the successful re-compilation of your design, you can re-run it by simply clicking the 'Run' button beside Sim 1 in the SIMULATION CONFIGURATION.

Run your design in the cloud

1. When you're ready to run your simulation in the cloud, click the 'Run in DSim Cloud' button next to the desired Simulation Configuration.

2. DSim Desktop automatically converts your local simulation to a job file and submits it to the cloud. You must be signed into your DSim Cloud account to submit a job to the cloud. A notification pops up indicating the status of your job submission. When it is complete, click the 'Show Jobs' button or in your DSim Desktop view, expand the JOBS section to see your job.

3. Expand your job to see the status of each task. Sometimes it may take a while (several minutes) for remote cloud resources to become available to run your job.

4. Once your job is complete, click the 'Download All Artifacts' button to retrieve your simulation artifacts.

5. A notification pops up indicating the status of your artifact download. When it is complete, click the 'Reveal in Explorer' button or in your VSC Explorer view, navigate to /simulation_scripts/_downloaded_artifacts/turbov-xxxxx/work.

6. Your VSC Explorer will open to the folder where your simulation artifacts were downloaded from your simulation in the cloud.

Next Steps

1. Play around with the DSim Desktop GUI. Right-click on the files in the VSC Explorer to see what options are available. The DSim Desktop options are prefixed with DSim Desktop:. Right-click on the files in the LIBRARY CONFIGURATION and SIMULATION CONFIGURATION to see what options are available.

2. Create your own projects for the intel_FPGA_turbov_0_example_design design:

• Separate the testbench file turbov_ul_top_tb.sv from the file list work_sv_filelist.txt and compile it by itself.
• Change the order of compilation to see how this affects your success.

3. Create and simulate your own designs.