User Guide: DSim Known Issues

Version: 20240923.0.0

All Language Reference Manual references are noted with the following abbreviations:

• SV-LRM : SystemVerilog Language Reference Manual IEEE Std 1800™-2023
• VHDL-LRM : VHDL Language Reference Manual IEEE Std 1076™-2008 or IEEE Std 1076™-2000

SystemVerilog

Limitations with forced variables and nets

A force/release statement on singular elements (selected with a constant) of unpacked arrays is supported. However, a force/release statement on unpacked unions, or elements thereof is not supported. The LHS expression of the assignment in the procedural force/release statement:

shall reference a non-random static variable or a net with a built-in net type:

• or shall be a constant indexing/field select thereof,
• or shall be a concatenation thereof

shall not involve a select operation in the LHS expansion where:

• the indexing is not constant
• the prefix type is a user-defined nettype
• the prefix type is an unpacked union
• the prefix type is a dynamically sized array

shall have a singular data type:

• except entire unpacked arrays, these may be forced/released

If a forced statement (active or inactive) is applied to a net/variable or part thereof, the following accesses to that net/variable are prohibited:

• Non-singular assignment such as:
• assignment to an unpacked array slice
• Mutating array methods (e.g. sort, shuffle)
• Randomize

SV-LRM Reference: 10.6.2 The force and release procedural statements

SystemVerilog Assertions

Description:

Use of an unsupported SVA element will be flagged as a compile-time error.

The following properties are not currently supported: accept_on, reject_on, sync_accept_on and sync_reject_on. All other property and sequence operators are supported.

Additional limitations on assertions are:

1. Only variables, nets, expressions and event expressions can be passed as arguments to named sequences and properties. Arguments or local variables of type sequence or property are not yet supported.
2. Recursive properties containing sample value functions, sequence methods or their own clocking event are not yet supported.
3. Assertion control system tasks (section 20.12 in the SV-LRM) for ON, OFF and KILL are supported, but those related to assert action tasks are not. User may use a compile time option -vacuous to control whether or not to execute an assertion's pass action on vacuous success.

4. VPI access to SVA elements (section 37) and Assertion API (section 39) are only partially supported:

   
   
   • a. VPI access to assertion related objects (sections 37.47 to 37.54) is limited to concurrent and immediate assert, assume and cover statements. Access to property inst, sequence inst, property declaration, sequence declaration, property expression and sequence expression is not supported.
   • b. Placing assertion system callbacks is supported only for cbAssertionSysInitialized reason.
   • c. Placing assertion callbacks is supported only for reasons cbAssertionStart, cbAssertionSuccess, cbAssertionVacuousSuccess and cbAssertionFailure.

5. Code coverage control and API (section 40) for assertions is not supported. Coverage information for concurrent assertions and immediate cover statements are always written to the coverage database.

   
   
6. A multiclocked sequence or property concatenating two possibly overlapping clock ticks may have a race condition if the ticks happen in different re-entries to the observe region during the same time step.
7. An initialization assignment to local variables is not supported for properties with multiple semantic leading clocks, though an equivalent property is supported as long as the local variable initialization is done outside the local variable declaration.
8. The evaluation of inout arguments to system tasks used in deferred assertion action blocks are not evaluated until the deferred time. All other input arguments, and inout arguments to non-system tasks and functions are evaluated immediately.

User may specify -no-sva command option to ignore any concurrent assertion statement, expect property statement, property declaration, and sequence declaration.

SV-LRM Reference: 16 Assertions

Specify Blocks

Zero Delay Glitch with two Specify Blocks

Description:

Zero delay glitches may occur on a net under the influence of two specify blocks: the first specify block is inside the module instantiated in another module which contains the second specify block.

In the higher level module, a transition may be scheduled on the net in the same time slot that a zero delay change is happening in the lower level module. Due to nondeterminism in the evaluation order of these two events, the net resolved value may experience a zero delay glitch.

SV-LRM Reference: 30 Specify Blocks

General SV-LRM Support

Description:

There are several parts of the SV-LRM which are not yet supported in dsim as indicated below.

SV-LRM Reference:

VHDL

VHDL 2008 support

VHDL-LRM: 2008

VHDL 2019 support

VHDL-LRM: 2000

The conditional analysis directives are supported. No other feature new to 2019 is supported.