User Guide: DSim Verilog Design and Verification Building Blocks

Modified on Thu, 11 Jul at 11:43 AM

User Guide: DSim Verilog Design and Verification Building Blocks

Compilation Unit Scope

For purposes of parsing and initial semantic analysis, DSim treats each file listed on the command line as a separate compilation unit, which also includes anything included from the file. If a top-level construct is unterminated at the end of a top-level file then a parse error will be reported.

Clause SV-LRM 3.12.1 requires that tools support both possible models for compilation-unit scope: one scope for the entire design, and one scope per compilation unit. Previous versions of DSim supported only the first model. Starting with 20201123 relase, both models are supported, selected by the -shared-unit-scope or -separate-unit-scopes respectively.

Given that the treatment of compilation-unit scope can vary from tool to tool, we recommend that compilation-unit scope not be used. All declarations outside design elements (modules, interfaces, etc.) should be put in packages.

Name Spaces

The definitions name space contains definitions for modules, interfaces, program blocks and primitives.

The module name space contains definitions of items that are encountered inside a module. In particular, it contains typedefs.

Generally speaking, two declarations cannot have the same name if they are to appear in the same name space. However, two declarations can have the same name if they appear in different name spaces. For example, it is legal to name a module the same as a variable. References to the module in a module instantiation are not ambiguous - such references are always to the definitions name space, whereas references to variables are always to the module and block name spaces.

There is an exception: it is possible to give an interface the same name as a typedef. If this name is used in a declaration of an interface port (or array thereof), it is ambiguous as to whether the interface or typedef is intended:


interface foo;

typedef reg [1:0] foo;

module mymod(foo f);


In this case, DSim will favor the module name space (or compilation-unit scope) and resolve the typedef first. This also means that DSim may not recognize interface names in contexts where they are illegal - the compiler will simply not check the definitions name space in such cases.

Time Value Rounding

DSim will warn if the value of a time literal is given with greater precision than the time precision in effect where it appears.

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