Block coverage closing implicit case defaults

Hi Charles, 

I definetly agree with you which is about not being cost efficent to create implicit case defaults if and only if given case parameter is not totally covered and if case parameter is totally covered then do not create implicit defaults. Also about not using explicit defaults is bad coding practice which ends up as lint problem. However, I have suggested ideas to come up with a solution. One of them is exluding lines from line coverage using pragmas as you said before and also I have suggested that controlling creation of implicit defaults and implicit elses for all over that run maybe using a run flag without identifying whether implicit defaults would be possible or not. Maybe you might also want to consider that idea because of being more feasible and cost efficent rather then identify every branch in coverage scope.

With that said, thank you all for time. 

While the example in question is simple, most examples will not be so.  In order to determine that all possible values are covered by the case statements, the simulator would have to do an evaluation of the solution space of the equation in the case statement.  I do not know how feasible it would be to statically evaluate the solution space and determine if there are possible values which would need a default statement.  Generally, it is bad coding practice to not have a default for a case statement.  What we need is to have the ability exclude lines from coverage consideration.

Hi David, 

Thank you for clarification 

> Can you confirm me about last comment I posted here.

Your understanding is correct: neither of them is available today.   That said, I am going to bring up the problem to an attention of our R&D.

Hi David, 

Simpliest code snippet I can share with you related with issue is that : 

module test_dut (input bit i_clk, 
                 output bit [1:0] state);
  
  bit [1:0] state_local;
  
  always @(posedge i_clk) begin
    case (state_local)
      'b00 : state_local = 'h1;
      'b01 : state_local = 'h2;
      'b10 : state_local = 'h3;
      'b11 : state_local = 'h0;
    endcase
  end
      
  assign state = state_local;
      
endmodule

module test_tb ();
  
  bit i_clk;
  bit [1:0] state;
  
  always #20 i_clk = ~i_clk;
  
  test_dut dut (.i_clk(i_clk),
                .state(state)); 
  
  initial begin
    #500ns;
    $finish;
  end
  
endmodule

case (state_local)
      'b00 : state_local = 'h1;
      'b01 : state_local = 'h2;
      'b10 : state_local = 'h3;
      default : state_local = 'h0;
endcase

case (state_local)
      'b00 : state_local = 'h1;
      'b01 : state_local = 'h2;
      'b10 : state_local = 'h3;
      'b11 : state_local = 'h0;
      default : state_local = 'h0;
endcase

Hi Deniz,

I understand the problem that you are facing.  Do you mind to share a code snippet, so that I may reproduce the problem on our end.

Hi Deniz. I have moved this post to the more appropriate forum, DSim -> Coverage.

Can you confirm me about last comment I posted here.

Hi David, 

Sorry for misunderstanding. What I am asking was "Even though a designer design a 'case' which covers all the possible values DSIM creates implicit case defaults to these cases and of course they are impossible the cover. I setup a test environment for giving you right info all the integral types which can be 2 state or 4 state and enumareted type cases is imposible the cover unless a designer makes for example 'FETCH' state in default which is highly unaccurate. To sum up, It is impossible the take %100 percentage line coverage from a case whom case variable type can be nearly everything unless 'default' construct is used for possible case variable expectation even if this is a common lint problem.

Some vendors have different approaches to these issue. So that's why I asked, is there an run_time option, pragma, directives or compile flags to control either implicit case creation or excluding a line from line coverage simply giving comment pragmas and as far as I understood neither of them is available today. 

I am closing the case.

Thank you 

> Do I have any option to exclude code block from line coverage ...

I do not understand your question.  If you are asking: 

• Do I have a way to instruct DSim to exclude any implicit default statement from line coverage?

As of today, it is not possible.  That is, any occurrence of an implicit default statement is included in line coverage.

That said, if you create a feature request, and enough people upvote it, we may put it on our roadmap.

--------------------------------------------------------------------------------
> Do I have any option to ... close automatic implicit case default creation in line coverage report

I do not understand your question.  If you are asking:

• How do I close line coverage for an implicit default statement?

Let's take a look at the following code snippet: 

logic [15:0] data;
logic [9:0] result;

case (data)
    16'd0: result = 10'b0111111111;
    16'd1: result = 10'b1011111111;
    16'd2: result = 10'b1101111111;
    16'd3: result = 10'b1110111111;
    16'd4: result = 10'b1111011111;
    16'd5: result = 10'b1111101111;
    16'd6: result = 10'b1111110111;
    16'd7: result = 10'b1111111011;
    16'd8: result = 10'b1111111101;
    16'd9: result = 10'b1111111110;
    // here is an implicit default statement
endcase

It is enough to exercise any data value outside of the [16'd0:16'd9] range.