I am struggling with dumping waves from a VHDL simulation. When I look at the waves, I'm getting Xs and Zs instead of 0s and 1s:
I have attached the relevant files (I think). I cannot find anything about this in the documentation.
(In fact, I have regressed to a simpler VHDL simulation. The one I started with didn't record any waveforms at all at the testbench level, despite there being various std_logic signals and std_logic_vector signals.)
I am struggling with dumping waves from a VHDL simulation. When I look at the waves, I'm getting Xs and Zs instead of 0s and 1s:
I have attached the relevant files (I think). I cannot find anything about this in the documentation.
(In fact, I have regressed to a simpler VHDL simulation. The one I started with didn't record any waveforms at all at the testbench level, despite there being various std_logic signals and std_logic_vector signals.)
Attachments (3)
counter.vhd
782 Bytes
countertb.vhd
5.16 KB
ex07.dpf
390 Bytes
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1 Comments
Shaun Luong posted about 2 months ago Admin
Not displaying VHDL signals properly in our Waveform Viewer is a known limitation which will be fixed in a future release.
See this post for details: https://help.metrics.ca/support/discussions/topics/154000634960
This limitation is documented in the DSim Desktop extension change log:
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