Shona Weldon posted
about 2 months ago
AdminBest Answer
This bug has been fixed in DSim version 20240422.7.0. Please upgrade DSim and confirm that it fixes your issue.
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Shaun Luongposted
28 days ago
Admin
The -sv option is required if the file extension is not .sv, as in your case. DSim will interpret .v files as Verilog and .sv files as SystemVerilog unless otherwise configured. See User Guide: DSim Input Filename Examples for details.
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M
Maciej Dudekposted
28 days ago
DSim requires `-sv` flag to be set to work
0 Votes
S
Shona Weldonposted
about 2 months ago
AdminAnswer
This bug has been fixed in DSim version 20240422.7.0. Please upgrade DSim and confirm that it fixes your issue.
0 Votes
S
Shona Weldonposted
about 2 months ago
Admin
We have found the issue, it will be fixed in our next release. I will post an update here when it is available.
0 Votes
S
Shona Weldonposted
about 2 months ago
Admin
Thank you for the specific command, I have been able to reproduce it and I'll look into the issue. One of the optimizations is mis-handling something in your test.
You could try running without optimizations off (add `-noopt` to the command line) as a short term work around. It's not a satisfactory solution however, because without optimizations larger designs will be slow in simulation.
How did you compile test.v? I am unable to reproduce your issue because of the following parsing errors which occur when I execute `dsim test.v` and `dvlcom test.v`:
Analyzing...
=E:[ParseError]:
Parser errors encountered at the following locations:
test.v:14:10 unrecognized tokens before '@'
test.v:16:18 unrecognized tokens before '<='
test.v:20:22 expected '.', '[', '('... instead of '<='
test.v:20:47 unrecognized tokens before ';'
Metrics DSim version: 20240422.6.0 (b:R #c:0 h:14d0e78ed1 os:msys2_)
Hi,
I was playing with DSim on the Linux system (DSim version 20240422.6.0)
and I found weird crash:
I've created small example that triggers this error.
Attachments (1)
test.v
562 Bytes
0 Votes
Shona Weldon posted about 2 months ago Admin Best Answer
This bug has been fixed in DSim version 20240422.7.0. Please upgrade DSim and confirm that it fixes your issue.
0 Votes
7 Comments
Shaun Luong posted 28 days ago Admin
The -sv option is required if the file extension is not .sv, as in your case. DSim will interpret .v files as Verilog and .sv files as SystemVerilog unless otherwise configured. See User Guide: DSim Input Filename Examples for details.
0 Votes
Maciej Dudek posted 28 days ago
DSim requires `-sv` flag to be set to work
0 Votes
Shona Weldon posted about 2 months ago Admin Answer
This bug has been fixed in DSim version 20240422.7.0. Please upgrade DSim and confirm that it fixes your issue.
0 Votes
Shona Weldon posted about 2 months ago Admin
We have found the issue, it will be fixed in our next release. I will post an update here when it is available.
0 Votes
Shona Weldon posted about 2 months ago Admin
Thank you for the specific command, I have been able to reproduce it and I'll look into the issue. One of the optimizations is mis-handling something in your test.
You could try running without optimizations off (add `-noopt` to the command line) as a short term work around. It's not a satisfactory solution however, because without optimizations larger designs will be slow in simulation.
0 Votes
Maciej Dudek posted about 2 months ago
I'm running it with
0 Votes
Shaun Luong posted about 2 months ago Admin
How did you compile test.v? I am unable to reproduce your issue because of the following parsing errors which occur when I execute `dsim test.v` and `dvlcom test.v`:
0 Votes
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