Working dsim verification environment crashes when I gave the flag called "-code-cov a". Before giving that coverage flag it compiles and simulates perfectly. The crash comes from CGModule.cpp line 354. There is a assert statement that fails and crashes program with flag "=F:[Crash]". The verification environment includes nothing special or too complicated. It includes standard UVM components and trans_items plus RAL model with frontdoor and backdoor access to check how dsim works with RAL model. Design is SystemVerilog. Detailed log file can be found inside attachments. Configuration of project can bee from dpf file which is given below :
# Note: The contents of this file are automatically generated.
This is a known issue. The current release will crash if you attempt to instrument the UVM library for code coverage.
Assuming you don't want to cover your testbench, a workaround is to instrument the RTL only. This can be done with -code-cov a-code-cov-scope-specs <file>. Example of a coverage specs file:
# Example code coverage specs: enable block coverage on DUT only
path tb.dut +b
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4 Comments
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Shaun Luongposted
4 months ago
Admin
@Deniz I have moved your post to DSim / Coverage as requested. I'll follow up with David to see when this known issue will be fixed.
1 Votes
D
Deniz Güzelposted
4 months ago
@David And also unfortunately I did open this case under wrong section and I can not change the scope of this case. That would be awesome if you carry this case under Dsim/coverage to build better forum. Thanks again and sorry about misplaced case opening.
0 Votes
D
Deniz Güzelposted
4 months ago
@David thanks for the answer I am closing the case.
0 Votes
D
David Jonesposted
4 months ago
AdminAnswer
This is a known issue. The current release will crash if you attempt to instrument the UVM library for code coverage.
Assuming you don't want to cover your testbench, a workaround is to instrument the RTL only. This can be done with -code-cov a-code-cov-scope-specs <file>. Example of a coverage specs file:
# Example code coverage specs: enable block coverage on DUT only
path tb.dut +b
Working dsim verification environment crashes when I gave the flag called "-code-cov a". Before giving that coverage flag it compiles and simulates perfectly. The crash comes from CGModule.cpp line 354. There is a assert statement that fails and crashes program with flag "=F:[Crash]". The verification environment includes nothing special or too complicated. It includes standard UVM components and trans_items plus RAL model with frontdoor and backdoor access to check how dsim works with RAL model. Design is SystemVerilog. Detailed log file can be found inside attachments. Configuration of project can bee from dpf file which is given below :
# Note: The contents of this file are automatically generated.
# Any changes made by hand may be overwritten.
version: '0.2'
work_dir: .
design_root_dir: .
simulations:
- name: run_regTest
options: >-
-top uvc.tb_top -L dut -L uvc +acc+b -waves waves.mxd -uvm 1.2
+UVM_NO_RELNOTES -sv_seed 365 -code-cov a
source_files:
- language: verilog
path: ./design.sv
library_name: dut
options: '-timescale 1ns/10ps'
- language: verilog
path: ./flist
library_name: uvc
options: '-uvm 1.2 +incdir+dir[+./.]'
file_list: relative-to-file
library_search_paths:
- $STD_LIBS\ieee93
I am using Windows 11 and Dsim version is 20240422.0.0
Attachments (1)
crash.log
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David Jones posted 4 months ago Admin Best Answer
This is a known issue. The current release will crash if you attempt to instrument the UVM library for code coverage.
Assuming you don't want to cover your testbench, a workaround is to instrument the RTL only. This can be done with -code-cov a -code-cov-scope-specs <file>. Example of a coverage specs file:
0 Votes
4 Comments
Shaun Luong posted 4 months ago Admin
@Deniz I have moved your post to DSim / Coverage as requested. I'll follow up with David to see when this known issue will be fixed.
1 Votes
Deniz Güzel posted 4 months ago
@David And also unfortunately I did open this case under wrong section and I can not change the scope of this case. That would be awesome if you carry this case under Dsim/coverage to build better forum. Thanks again and sorry about misplaced case opening.
0 Votes
Deniz Güzel posted 4 months ago
@David thanks for the answer I am closing the case.
0 Votes
David Jones posted 4 months ago Admin Answer
This is a known issue. The current release will crash if you attempt to instrument the UVM library for code coverage.
Assuming you don't want to cover your testbench, a workaround is to instrument the RTL only. This can be done with -code-cov a -code-cov-scope-specs <file>. Example of a coverage specs file:
0 Votes
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