Jobs: Task Dependencies

Modified on Sun, 23 Jun at 9:56 AM

Jobs: Task Dependencies

Job tasks are executed in parallel unless they contain the depends property. The value of the depends property, given as an array of task names, specifies which task(s) must complete before the current task can be executed. A single job can have multiple tasks linked by a Directed Acyclic Graph (DAG), resulting in task dependencies. Each task can execute multiple simulator commands. This diagram shows a job with multiple tasks with dependencies:



Task elaborate depends on task compile. Tasks sim1 to sim5 depend on task elaborate.


All files required to execute a task with dependencies must be passed to it by a previously executed task as working inputs inputs.working. Tasks pass files to other tasks as working outputs outputs.working. All working inputs and outputs are intermediate files that are removed upon job completion, ie. they are not available for download.


Let's examine the following tasks from carry_lookahead_adder.yml to see the task dependencies:


 

- name: compile-sv
  depends: [sim-vhdl-sv]
  commands:
    - dsim -genimage image_sv -F SystemVerilog/sim/filelist.txt +acc+b
  inputs:
    working:
      - name: sim-vhdl-sv.source
        path: ./
  outputs:
    artifacts:
      - name: log-sv
        path: dsim.log
    working:
      - name: image-sv
        path: dsim_work/image_sv.so
- name: sim-vhdl-sv
  compute_size: s8
  mdc_work: VHDL_SystemVerilog/sim/
  commands:
    - dvhcom -F filelist_VHDL.txt
    - dvlcom -F filelist_SV.txt
    - dsim -top work.carry_lookahead_adder_tb +acc+b -waves waves_vhdl_sv.mxd
  outputs:
    working:
      - name: source
        path: ./

 

The task compile-sv depends on the task sim-vhdl-sv and requires all the files from the local workspace. The files are passed to inputs.working of compile-sv as sim-vhdl-sv.source since the required outputs.working of sim-vhdl-sv is source. The path / indicates all folders and files of the remote work directory.


 

- name: run-sv-1
  depends: [compile-sv]
  commands:
    - dsim -image image_sv -waves waves_sv_1.vcd -sv_seed 1
  inputs:
    working:
      - name: compile-sv.image-sv
        path: dsim_work/image_sv.so

 

The task run-sv-1 depends on the task compile-sv and requires only the image file generated by it. The file is passed to inputs.working of run-sv-1 as compile-sv.image-sv from the outputs.working image-sv of compile-sv. The path dsim_work/image_sv.so is relative to the remote work directory.


 

- name: run-sv-2
  depends: [compile-sv]
  commands:
    - dsim -image image_sv -waves waves_sv_2.mxd -sv_seed 2
  inputs:
    working:
      - name: compile-sv.image-sv
        path: dsim_work/image_sv.so
  outputs:
    artifacts:
      - name: waves-sv-2
        path: waves_sv_2.mxd
      - name: log-sv-2
        path: dsim.log
- name: run-sv-3
  depends: [compile-sv]
  commands:
    - dsim -image image_sv -waves waves_sv_3.mxd -sv_seed 3
  inputs:
    working:
      - name: compile-sv.image-sv
        path: dsim_work/image_sv.so

 

The tasks run-sv-2 and run-sv-3 also depend on the task compile-sv. This is how you can compile only once and run many times using the same image.


 

- name: sim-vhdl
  depends: [run-sv-3, sim-vhdl-sv]
  commands:
    - dvhcom -F VHDL/sim/filelist.txt
    - dsim -top work.carry_lookahead_adder_tb +acc+b -waves waves_vhdl.mxd
  inputs:
    working:
      - name: sim-vhdl-sv.source
        path: ./

 

Similarly, task sim-vhdl depends on tasks run-sv-3 and sim-vhdl-sv. This is how you can specify the order of task execution.


So instead of all tasks being executed in parallel, they will be executed in this order:


  1. sim-vhdl-sv


  2. compile-sv


  3. run-sv-1, run-sv-2, and run-sv-3


  4. sim-vhdl


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